1. Field of the Invention
The present invention relates to a differential amplifier including a CMOS circuit.
2. Description of the Related Art
In order to widen an input voltage range of a differential amplifier, a technology of providing a differential input circuit including an N-type MOS transistor and a differential input circuit including a P-type MOS transistor has been known.
FIG. 4 illustrates a conventional input rail-to-rail differential amplifier.
The conventional input rail-to-rail differential amplifier includes: a non-inverting input terminal 143; an inverting input terminal 144; a differential amplifier circuit including P-type MOS transistors 107 and 108, N-type MOS transistors 101 and 102, and a constant current source 121; a differential amplifier circuit including P-type MOS transistors 103 and 104, N-type MOS transistors 113 and 114, and a constant current source 122; a constant current source 124 for causing currents to flow into the P-type MOS transistors 107 and 108; and an output circuit provided between the differential amplifier circuits and an output terminal 145. The output circuit includes: an output driver including a P-type MOS transistor 117 and an N-type MOS transistor 118; and phase compensation capacitors 151 and 152.
When a voltage close to a power supply voltage is input to the non-inverting input terminal 143 and the inverting input terminal 144, the P-type MOS transistors 103 and 104 are turned off, but a differential input circuit including the N-type MOS transistors 101 and 102 operates. When a voltage close to a ground (GND) voltage is input to the non-inverting input terminal 143 and the inverting input terminal 144, the N-type MOS transistors 101 and 102 are turned off, but a differential input circuit including the P-type MOS transistors 103 and 104 operates. Therefore, an input rail-to-rail operation is realized. Cascode voltages are applied to terminals 131, 132, 133, and 134.
Gate voltages of the P-type MOS transistor 117 and the N-type MOS transistor 118 of the output driver connected to the output terminal 145 are controlled to suitable voltages by a P-type MOS transistor 115 and an N-type MOS transistor 116. In a case where a current flows through a P-type MOS transistor 110 and an N-type MOS transistor 112, even when there is no load current in the output terminal 145, a current flows into the transistors of the output driver, to thereby implement a class-AB output operation (see, for example, “Design of analog CMOS integrated circuit”, Second volume, p. 396).
As described above, even in a case where the voltage of the non-inverting input terminal 143 is changed between the GND voltage and the power supply voltage, any one of the differential input circuit including the P-type MOS transistors and the differential input circuit including the N-type MOS transistors operates, and hence the input rail-to-rail operation is possible.
However, the differential amplifier described above has a problem that a value of the current flowing through the transistors of the output driver changes depending on a voltage level input to the non-inverting input terminal 143 and the inverting input terminal 144.
FIG. 5 illustrates current values at respective nodes in a case where the voltage of the non-inverting input terminal 143 is changed in the differential amplifier illustrated in FIG. 4.
In order to implement the class-AB output operation, a current is required to flow through the P-type MOS transistor 117 and the N-type MOS transistor 118 even in a case where the load current does not flow into the output terminal 145.
The P-type MOS transistor 115 is provided to adjust a gate-source voltage of the P-type MOS transistor 117 so that a current continuously flows into the P-type MOS transistor 117. Therefore, a current value of the P-type MOS transistor 117 is determined based on a threshold value of the P-type MOS transistor 115 and a flowing current value. The N-type MOS transistor 116 is provided to adjust a gate-source voltage of the N-type MOS transistor 118 so that a current continuously flows into the N-type MOS transistor 118. Therefore, a current value of the N-type MOS transistor 118 is determined based on a threshold value of the N-type MOS transistor 116 and a flowing current value. A current flowing through the P-type MOS transistor 110 is divided into two by the P-type MOS transistor 115 and the N-type MOS transistor 116. A current flowing into the P-type MOS transistor 110 is obtained by subtracting a current value of the N-type MOS transistor 102 from a current value of the P-type MOS transistor 108 connected to the constant current source 124 for current mirror.
As described above, the current value of the N-type MOS transistor 102 reduces when the voltage of the non-inverting input terminal 143 is close to the power supply voltage. Therefore, the current flowing into the P-type MOS transistor 110 increases, to thereby significantly change the value of the current flowing through the P-type MOS transistor 117 and the N-type MOS transistor 118. Thus, a value of an output capacitor which may be connected to the output terminal 145 to be drivable changes, and hence phase compensation is difficult. That is, the phase compensation capacitors 151 and 152 are required to have a large capacitance with a margin.